1. Field of Invention
The present invention relates to a structure of a Phase Lock Loop (PLL) and a Phase Lock (PL) method, particularly a method for stabilizing output frequency of PLL and an apparatus thereof.
2. Description of the Related Art
That the development of phase lock loops, has been taken a long time and remains an important issue in the electrical field nowadays because the phase lock loops are widely used with prospects for sustainable development. Many features of the phase lock loop on its merits can be continuously improved, advanced, such as: higher frequency upper limit, better stability, larger range of bandwidth and shorter locking-time.
All in all, a PLL essentially uses an oscillating source with negligible frequency-variation as the reference and drives variable frequency components by means of a feedback of a closed loop control system, so that the different frequency components can be synchronized with the oscillating source in a fast and durably stable manner, i.e., is phased being locked.
FIG. 1 is a circuit block diagram of a conventional PLL, where the configuration of a PLL is comprised of five electronic sub-systems: a phase/frequency detector PFD, a charge pump CP, a loop filter LF, a voltage control oscillator VCO and a frequency divider FD. The phase/frequency detector PFD is used for detecting the difference phase between a reference signal REF and a feedback signal DS after dividing frequency and for converting the comparison result into two digital signals, i.e. a pull-up signal DH and a pull-down signal DL, for output. The charge pump CP is for converting the two digital signals into a control voltage CV for output. The loop filter LF is used for filtering out the high-frequency composition from the control voltage. The voltage control oscillator VCO is used for converting the control voltage into an oscillating signal VO for output. The frequency divider FD serves for reducing the frequency and feedbacking the frequency-reduced signal to the phase/frequency detector PFD for comparison with the reference signal REF.
During no reference signal REF available, the Phase/Frequency Detector PFD detects such reference signals, and the pull-up signal DH and the pull-down signal DL outputs logi-0 and logic-1, respectively. When the charge pump CP receives logic-O of the pull-up signal DH and logic-1 of the pull-down signal DL, the control voltage CV is enabled to drop continually. As a result, the frequency of the oscillating signal VO output from the voltage control oscillator VCO is accordingly dropped. As the reference signal REF resumes the original level, the charge pump CP resumes the original value of the control voltage CV. Thus, the frequency of the oscillating signal VO output from the voltage control oscillator VCO resumes as well.
In the event of an intermittent signal, such as: a color synchronic signal (burst signal) or conducting an operation of restoring data, the control voltage CV of a conventional PLL varies frequently and the charge pump CP to charge-discharge the capacitor of the loop filter LF frequently. Thus, changes in the output frequency increase with more power consumption.